1. Field of the Invention
The present invention relates to the field of processors. More specifically, the present invention relates to the art of instruction execution practiced on processors.
2. Background Information
Prior art approaches to instruction execution practiced by processors can be broadly classified into three approaches based on the manner operand storage is handled. Broadly defined, the three approaches are stack based approach, accumulator based approach and register based approach. Stack, accumulator and registers are different functional forms of temporary storage medium employed in processor datapaths, which in addition to the temporary storage medium, includes arithmetic logic units (ALU) and so forth. Register is characterized by their symbolic designations through register identifiers, i.e. R1, R2 and so forth. The term processor as used herein in the present specification is intended to include micro-controllers (MCU), digital signal processors (DSP), general purpose microprocessors (uP), and the like, whereas the term instruction as used herein is intended to include macro-instructions visible to programmers or compiler writers as well as micro-instructions, micro-operations, or primitive operations and the like that are not visible to programmers and compiler writers.
In the case of the stack based approach, one of the source as well as the destination operand of an instruction are implicitly defined to be located at the top of the stack, whereas, in the case of the accumulator based approach, one of the source as well as the destination operand of an instruction are implicitly defined to be located in the accumulator. Typically, the other source operand is located in a register. In the case of the register set based approach, the source and the destination operands of an instruction are either located in registers or in memory locations. While registers are specified by their identifiers, memory locations, whether cached or not, are specified by either physical or virtual addresses, depending on the manner in which memory is managed.
While the stack based approach enjoys the advantage of providing a simple model for expression evaluation, and short instruction, the approach suffers from at least the disadvantages of forcing all the operands onto the stack, and yet not being able to randomly access the pushed down operands in the stack, resulting in inefficient coding. As to the accumulator approach, while it minimizes the internal states of a processor, and provides for short instructions, it also suffers from at least the disadvantage of very high memory traffic, since the accumulator is the only temporary storage. The register based approach has the advantage of being the most general model for code generation, however, because of the access and related circuitry required to support a register, most prior art register based processors tend to provide only a limited number of registers, resulting in a relatively small working set. The disadvantage becomes especially limiting for heavily pipelined super-scalar processors.
Thus, a more efficient and effective approach to instruction execution without some of the disadvantages of the prior art approaches is desired.